Design Analysis of Wallace Tree based Multiplier using Approximate Full Adder and Kogge Stone Adder

Abstract

Attaining very fast digital devices with reduced power utilization is an important interest to the VLSI circuit designers and manufacturers. For the most part computation functions are carried out using the multiplier, where it is found to be more power consuming component in the electronic circuits. Eventually, the operation of multiplication has been carried out by the process of shift and add method. Due to the enhancement among various adders, which paved the way for the increase in execution rate of the multipliers. Parallel multiplication algorithms often use combinational circuits and don't contain feedback structures. The circuit is developed utilizing VHDL and functions were validated based on the simulations obtained utilizing Xilinx. In this project, the improvement in WTM using the KSA and the Modified Approximate Full Adder concepts is done. The Simulations are done Utilizing Xilinx ISE 14.7. The multiplier circuit covers about 27% of overall available area. The power obtained from the circuit is observed to be 0.037w.