Design an Area Efficient Kogge Stone Adder using Pass Transistor Logic

Abstract

In recent technologies of Electronics applications, Adder is an important source of any devices such as DSP, VLSI applications. For which, many electronics application devices used the high speed adders namely Parallel Prefix Adder (PPA). Generally, PP Adders have less delay due to its less waiting time of carry for next addition. But the area consumption is more, in which the performance of the adders will decrease for higher order bits' addition. This paper is to design an area efficient Kogge Stone PPA which performs the parallel arithmetic operations in CMOS applications and analysed the design based on the parameters like area and power individually. The proposed area efficient KSA design used the Pass Transistor Logic (PTL) and analysed the performance of particular design. The Performance results of PTL with PP-KSA design used the reduce number of MOS devices which yields less area consumption compared to basic design of 4-bit PP-KSA. Entire analysis results of these designs can be done in Microwind CMOS tool.