Abstract
As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.
Highlights
Image Segmentation, MRI, Contourlet transform, Active contours. As it was discussed in my previous paper [7], FPGA is emerging as a rapid prototype for its several advantages as was listed [7]
Both RISC & CISC Processor Architecture have their own merits & demerits & neither RISC nor CISC standalone Processor can produce a complete solution to the present day computational needs, there is a strong need of Hybrid Processor
I have evolved a fully scalable and open-ended Processor architecture for basic popular instructions of the processor that can be improvised into a complex generation multi core Processor
Summary
As it was discussed in my previous paper [7], FPGA is emerging as a rapid prototype for its several advantages as was listed [7]. This means, better the architecture design, powerful the instructions. Instruction based (Bottom up approach): here the approach is to list out the most used instructions of popular processors & implement them one by one. By putting all these implementation of instructions together, will emerge architecture at the top level. In this approach incremental growth of instruction implementation will lead to mega processor architecture. Example: Video processor, audio processor, mobile processor, data acquisition, instrumentation & measurements – all these applications utilize processors only for high speed data processing, dedicated fixed functions or instructions
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