Design & Comparison of 32-bit CSLA with Hybrid Logic

Abstract

Adders are used as a basic building element in a variety of computing units and processors. Carry select adder (CSLA) comes under one of the simplest and fastest multi-bit adders. In this study, we examine the results of designing CSLA utilizing two logic systems: CMOS and hybrid logic. Area and power are two critical issues in digital circuit design and synthesis of VLSI circuits, both of which depend on various parameters. The design of the proposed CSLA consists of Ripple Carry Adder (RCA), Binary Excess-1 converter (BEC), and 10:5 MUX. The circuits of XOR/XNOR, Full Adder, and proposed XOR/XNOR-based 32-bit CSLA are explored with hybrid logic. Unlike traditional CMOS-based CSLA, the proposed hybrid CSLA has an optimized low power and delay up to 7.9 μW and 0.01860 ns respectively. Furthermore, the transistor count is reduced to 1166, resulting in a reduction in size. The simulations have been done on cadence virtuoso and their performance parameters like transistor count, power, and delay are analysed. Technology Models of 45 nm are used to perform simulation results that show the circuit proposed with hybrid logic has superior speed and power against other circuits’ designs.