Descending Order Thermal Distribution Partitioning Algorithm for Flip-Chip Packaged 3-D ICs to Improve Heat Sinking and Reduce TSV Count

Abstract

As the size of metal–oxide semiconductor field-effect transistors (MOSFETs) is shrinking, there are new challenges at different stages of very-large-scale integration (VLSI) design flow. Several devices are densely placed compared to the older counterparts. 3-D integrated chip (3-D IC) packaging is one of the famous packaging technologies where in IC contains multiple dies having various modules or subsystems interconnected through silicon via TSVs. One of the major challenges in 3-D IC packaging is thermal management. This article proposes a descending order thermal distribution (DOTD) partitioning algorithm that helps to improve heat sinking in flip-chip based 3-D ICs along with reducing the number of TSVs. The proposed algorithm is run on thermal benchmark circuits from VLSI Computer-Aided Design (CAD) Lab of the University of California and results are compared with different partitioning algorithms. It shows that the proposed partitioning algorithm gives better thermal distribution facilitating improved heat sinking in 3-D ICs along with up to 14.54% reduction in TSV.