Dependence of Lateral Straggle Parameter on DC, RF/Analog, and Linearity Performance in SOI FinFET

Abstract

FinFET provide themselves as a strong candidate for low-power applications. However, the enactment of a device depends upon the precision of fabrication process. The ion implantation technique of source/drain region extends towards the channel region and affects the device performance. In this paper, the DC and short channel performances like transfer characteristic, output characteristic, Subthreshold Swing (SS), threshold voltage (V T), and current ratio (I on/I off) of SOI FinFET are reported for the variation in lateral straggle parameter (σ) from 0 to 5 nm. The effect of lateral straggle on various RF/analog figure of merits (FOMs) like transconductance (g m), output conductance (g d), intrinsic gain (g m/g d), gate capacitance (C gg), cut off frequency (f c), and gain frequency product (GFP) are presented for SOI FinFET. Furthermore, the linearity performance such as higher-order harmonics (g m2, g m3), voltage intercept point (VIP2, VIP3), input intercept point (IIP3), intermodulation distortion (IMD3), and 1-dB compression point are investigated by varying the lateral straggle from 0 to 5 nm. Results reveal that ION = 0.526 mA, g m = 0.507 mS, and f c = 3 THz are obtained at σ = 5 nm, whereas, VIP2 = 27.5 V and VIP3 = 20.2 V are observed at σ = 0 nm.