Demonstration of Split-Gate Type Trigate Flash Memory With Highly Suppressed Over-Erase

Abstract

The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ) variations before and after NOR-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CG</sub> ) of 176 nm show much smaller Vt distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) is higher than 3.1 V even the L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CG</sub> was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled NOR-type flash memory with highly suppressed over-erase.