Demonstration of scaling and monolithic stacking for higher integration of integrated circuit using c-axis aligned crystalline oxide semiconductor FET

Abstract

C-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs exhibit extremely low off-state leakage current and thus are suitable for low-power devices. Furthermore, CAAC-OS FETs can be integrated in the back end of line process and are promising as memory devices. For higher integration using the CAAC-OS FETs, we examined scaling and monolithic stacking. In addition, we present a 3D dynamic random access memory prototype, which is formed using three-layer monolithically stacked CAAC-OS FETs on a Si-CMOS and exhibits long-term data retention owing to the ultralow off-leakage current. These techniques will contribute to higher speed and integration of memory devices.