Abstract
Controlling the erase speed of a NAND flash is one of the challenges in memory technology. As the planar NAND flash has evolved to the vertically integrated gate-all-around (GAA), the number of stacks of word-lines (WL) was increased for better packing density. However, potential transfer through the silicon substrate or metal bit-line (BL) is insufficient with the increased number of stacks. Hence, we propose a novel V-NAND structure including multi-layered macaroni filler. The proposed macaroni filler is composed of a dielectric outer layer and a metallic core layer. The metallic core layer makes back-biasing is possible in V-NAND. As a result, erase speed can be improved without large modification of fabrication process or device layout.
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