Abstract
In this paper, a new technique is proposed for multiplication of two sampled low frequency analog signals and the result is in digital form. Out of the two signals, one signal is fed to the input of typical second order, ΔΣ Modulator (DSM). The operating period of the DSM circuit is varied directly in proportion to the absolute amplitude of the second analog signal. In this case, the average value of the digital output of quantizer is equal to the product of the analog signals in each sampling period. The dynamic range of input signals and the accuracy of proposed multiplier are better than the conventional CMOS multipliers.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
