Delay Handling Method in Dominant Pole Placement Based PID Controller Design

Abstract

Time delay handling is a major challenge in dominant pole placement design due to variable number of poles and zeros arising from the approximation of the delay term. This paper proposes a new theory for continuous time PID controller design using a dominant pole placement method mapped on to the discrete time domain with an appropriate choice of the sampling time to convert the delays in to finite number of poles. The method is developed to handle linear systems, represented by second-order plus time delay (SOPTD) transfer function models. The proposed method does not contain finite-term approximations such as various orders of Pade, for handling the time delays, which may affect the number and orientation of the resulting poles/zeros. Effectiveness of the proposed method have been shown using numerical simulations on nine SOPTD test-bench processes and another six challenging processes including single, double integrators, and process with zero damping.