Delay and current estimation in CMOS gates using collapsing

Abstract

We previously introduced an analytical model to compute the delay and the maximum supply current in CMOS inverters [1–3]. In this paper we extend our modelling to include static CMOS logic gates, using a collapsing technique which reduces the gate to an equivalent inverter. The technique deals not only with the input signal transition times and relative delays, but also with the position of the input in the case of series-connected MOSFETs. Although the reduction process is simple, it does not result in a significant accuracy penalty. The speed for calculating the delay and the maximum supply current in CMOS combinational circuits approaches four orders of magnitude better compared to HSPICE [4] simulation, while the improvement for computing the current waveform approaches three orders.