Abstract
A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.
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