Degradation of the Si-SiO/sub 2/ interface in MOSFETs with oxides in the 1-2 nanometer range under low field electrical stress

Abstract

In this work, the degradation of the Si-SiO/sub 2/ interface under low field electrical stress in MOSFETs with oxides thickness, d/sub ox/, between 2.3 and 1.2 nm is investigated for the first time. This is done using a charge pumping (CP) technique proposed recently and which allows the measurement of Si-SiO/sub 2/ interface trap characteristics, i.e. trap densities, D/sub it/, and trap cross sections, /spl sigma//sub e,h/, in such devices. The D/sub it/ values are discussed with regard to those obtained using stress induced leakage current (SILC). A much larger degradation rate is found when measured using SILC with regard to CP. The trap cross sections do not vary significantly during the stress. This likely results from the relatively small D/sub it/, variations.