On the SILC mechanism in MOSFET’s with ultrathin oxides

Abstract

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I g ( V g ), characteristics is thought to flow through Si–SiO 2 interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO 2 interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.