Degradation of Amorphous Silicon Thin Film Transistors Under Negative Gate Bias Stress

Abstract

Degradation of amorphous silicon thin-film transistors under negative gate bias stresses is systematically investigated. It is found that both state creation and hole trapping contribute to device threshold voltage Vth shifts. For direct-current stresses, state creation dominates in low-stress amplitude conditions, whereas hole trapping could dominate the second-stage degradation in high-stress amplitude conditions. For alternating-current stresses, it is found that domination of state creation or hole trapping mechanisms depends on stress frequency f, temperature, amplitude, and stress time. As a result, different turnaround phenomena of Vth degradation are observed. Both state creation and hole trapping mechanisms are enhanced by higher stress temperatures and amplitudes. Based on an RC delay model, both f- and duty-ratio-dependent degradation under low-f stress conditions can be understood, whereas a recovery phenomenon under high- f stress conditions can be explained by the hole trapping/emission mechanism. Device leakage current Ioff decreases under low-f stress but increases under high- f stress. State creation is considered responsible for the Ioff reduction, whereas hole injection is considered responsible for the Ioff increase.