Abstract
DNW-induced latch-up characteristics and their temperature-dependence are investigated in bulk FinFET technology. DNW-enclosed NMOS in PNPN and PNPNPN structures causes low latch-up immunity with detrimental high-temperature degradation. Varied methods are explored for holding voltage improvement. In summary, the shunting-resistance reduction through process-design co-optimization plays a critical role in solving DNW-induced latch-up challenges in FinFET technology.
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