Decimation filter of the delta-sigma analog-to-digital converter with ternary data encoding

Abstract

The results of the development of a decimation filter of an analog-to-digital converter with ternary data encoding are presented. The filter reduces the clock frequency of the delta-sigma modulator of 100 MHz by a factor of 27. The proposed circuit engineering solutions are designed for manufacturing using the standard 0.18 μm MOS technology and the bipolar supply of ±0.9 V. The performance capability of the circuits is confirmed by the results of functional and circuit simulation using MatLab and Cadence Design Systems software.