Dead Time Optimization in a GaN-Based Buck Converter

Abstract

A gallium nitride (GaN) field effect transistor can provide superior performance over a Si- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> due to its low <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance and low junction capacitances. However, a GaN-based converter exhibits higher dead time loss during reverse conduction. Thus, to improve the efficiency, dead time optimization is required. This article proposes simple models for dead time optimization in a GaN-based buck converter under different load conditions. The proposed models are analytical in nature compared to the conventional models available for Si-based converters. A buck converter prototype is designed using a 100 V GaN device (GS61008P from GaN Systems) and the proposed analytical model-based dead time optimization techniques are validated experimentally. The proposed modeling techniques can be extended for other GaN-based dc–dc converters.