DDR Debug Methodology for Board Design Quality and System Robustness

Abstract

System performance is a major indicator of a workstation or server. Besides the CPU’s (Central Processing Unit) computing power, the DRAM (Dynamic random-access memory) used in the memory system has a direct impact on the performance. To provide high bandwidth and large memory space, the memory system must operate in a high frequency and the system must have as many DRAM slots as possible, respectively.DDR4 (Double Data Rate 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation) has been introduced since 2014 and the current Intel® Xeon® D SoC (System-on-Chip) platform supports it to be operated in 2933 MT/s (Mega Transfers per Second) with two DRAM modules populated in a channel (2 DPC). Through the capability of supporting multiple channels (e.g., 4 channels), a system can support up to several Tera bytes of memory (e.g., 4x2x128 Giga Byte = 1 Tera Bytes).From system designer’s point of view, it is vital to test the robustness of the memory system in the EV (Electric Validation) phase of the design cycle. To achieve the goal, Intel not only asks designers to conduct “system test” by running test tools but also provides the “Intel Rank Margining Tool (RMT)” to help designer to understand how much eye height and eye width “margin” exist before the memory system run into issue. Since a severe low margin usually leads to a respin of the mainboard, both test and debug activities are critical to ensure the quality of the system design.In this paper, a systematic and scientific debug methodology is proposed and demonstrated to debug the low margin scenario.