DC power limitation of the heterojunction bipolar transistor with dot geometry: Effect of base potential distribution on thermal runaway

Abstract

The d.c. power limitation of a conventional HBT with dot geometry was studied theoretically using combined electro-thermal and transmission line models. In most cases, the thermal runaway occurs at a power level lower than that set by the intrinsic electronic property of the device. The dependence of the d.c. thermal runaway threshold power density, P max, on the emitter dot radius and emitter ballast resistance was calculated. Increasing emitter dot radius lowers P max. Although ballast resistance increases P max, the effect reduces as the emitter dot radius increases. This is caused by the non-uniform potential distribution in the base layer. When thermal runaway is considered, the nonuniform base-emitter potential offsets the improvement of the power handling capability by the physical ballast resistance. Conventional HBTs with a large radius (greater than 4 μm) exhibit a small P max caused by thermal effect. This threshold power density can be increased drastically by using the thermal shunt technique.