DC cancellation in the single-bit domain using ternary filtering

Abstract

A structure for single-bit DC blocking is presented. This type of DC blocker is useful in practice to improve the stability and dynamic range of single-bit systems. The DC blocker is essentially a ternary filtering structure whose input and output are both assumed to be sigma–delta modulated bitstreams. Two techniques have been utilised to design the ternary filter to allow for implementation and performance comparison. Performance is tested for different kinds of single-bit format input signals, including sinusoidal, FM and AM–FM signals. The proposed DC blocker contains no multipliers and can easily be implemented with FPGA technology.