Abstract

Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age - the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.

Highlights

  • Over the past decade, the capacity of NAND flash memory has been increasing continuously, as a result of aggressive process scaling and the advent of multi-level cell (MLC) technology

  • We propose Retention Failure Recovery (RFR), a new offline error recovery technique that identifies fast- and slow-leaking cells and determines the original value of an erroneous cell based on its leakage-speed property and its threshold voltage

  • Our evaluations show that RFR can effectively reduce average RBER by 50%, essentially doubling the error correction capability, which allows for the recovery of data otherwise uncorrectable by error-correcting codes (ECC) (Sec. 5)

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Summary

Introduction

The capacity of NAND flash memory has been increasing continuously, as a result of aggressive process scaling and the advent of multi-level cell (MLC) technology. As flash density increases, flash memory cells become more vulnerable to various types of device and circuit level noise [1][2] – e.g., retention noise [2][3][4][5][6], read disturbance noise [5], cellto-cell program interference noise [2][7][8], and program/erase (P/E) cycling noise [2][9] These are sources of errors that can significantly degrade NAND flash reliability. The threshold voltage (Vth) of a flash cell can be formulated as [15]: Vth Vthi ( QFG ) / Cpp (1)

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