Abstract
This paper presents a hardware processor for 100 Gbps wireless data link layer. A serial Reed-Solomon decoder requires a clock of 12.5 GHz to fulfill timings constraints of the transmission. Receiving a single Ethernet frame on a 100 Gbps physical layer may be faster than accessing DDR3 memory. Processing so fast streams on a state-of-the-art FPGA (field programmable gate arrays) requires a dedicated approach. Thus, the paper presents lightweight RS FEC engine, frames fragmentation, aggregation, and a protocol with selective fragment retransmission. The implemented FPGA demonstrator achieves nearly 120 Gbps and accepts bit error rate (BER) up to 2e-3. Moreover, redundancy added to the frames is adopted according to the channel BER by a dedicated link adaptation algorithm. At the end, ASIC synthesis results are presented including detailed statistics of consumed energy per bit.
Highlights
The fastest wireless technology available, based on wireless LAN 802.11ac (5 GHz) and 802.11ad (60 GHz), achieves data rates of “only” 7 Gbps [1]
Receiving a single Ethernet frame on a 100 Gbps physical layer may be faster than accessing DDR3 memory
If the retransmission process is taken into consideration (ARQ), the probability of successful transmission of a payload encapsulated into smaller frames is higher than probability of transmission of the same payload encapsulated into longer frames
Summary
The fastest wireless technology available, based on wireless LAN 802.11ac (5 GHz) and 802.11ad (60 GHz), achieves data rates of “only” 7 Gbps [1]. This paper is related to End2End100 project and cooperates with other proposed projects of the DFG SPP1655 [2]. This group of projects will investigate a complete wireless 100 Gbps system at terahertz frequencies (∼240 GHz). This paper describes research on the data link layer part of the demonstrator. Within the last three years, a few new approaches for 100 Gbps physical layer (PHY) have been proposed. To perform 100 Gbps transmissions, more than a fast PHY and baseband is required. As a result of our work an FPGA based data link layer processor is presented. The implementation uses link adaptation methods and process ∼117 Gbps of user data
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
