Abstract
This paper describes the design and Field Programmable Gate Array (FPGA) based 4 × 4 breadth heuristic Multiple-Input—Multiple-Output (MIMO) decoder using 16 and 64 Quadrature Amplitude Modulation (QAM) schemes. The intention of this work is to observe the performance of Candidate Execution with Low Latency Approach for soft MIMO detector in FPGA (CELLA). The Smart Ordering and Candidate Adding (SOCA), Parallel Candidate Adding (PCA) and Backward Candidate Adding (BCA) give better performance in terms of Bit Error Rate (BER) or chip level service. In order to attain both BER and FPGA level performance in a single system, CELLA is developed in this work. Simulation and experimental results demonstrate the effectiveness of the proposed work under the system 4 × 4 MIMO-OFDM employing 16 QAM and 64 QAM. The proposed experiment is implemented in Xilinx Virtex 5 C5VSX240T. The performance results, in terms of FPGA level 76% slice reduction, 58.76% throughput improvement, 75% power reduction and 87% latency reduction, are achieved. The BER performance is observed and compared with the conventional algorithms. Thus, the proposed work achieves better outcome than the conventional work.
Highlights
In today’s data-rich world, Multiple Input Multiple Output (MIMO) has become an energetic element of wireless communication standard for high data rate communications
This deals with the minimized consumption of the nodes with the above-described elements. It works in a conventional way but with the reduction in the consumption of nodes. This makes the best performance in the usage of nodes and when it is seen microscopically, the motto of the power reduction is achieved at the rate of 141 mw and 40 mw, which correspond to the 64 Quadrature Amplitude Modulation (QAM) and 16 QAM, respectively
The performance analysis at Field Programmable Gate Array (FPGA) level attains 76% slice reduction, 58.76% throughput improvement at 20 db, 75% power reduction and 87% latency reduction when compared to the conventional work
Summary
In today’s data-rich world, MIMO has become an energetic element of wireless communication standard for high data rate communications. The two major problems of the List Sphere Decoder (LSD) are variable complexity and the sequential nature of its tree search To overcome these issues, a Fixed-complexity Sphere Decoder (FSD) is modified as List FSD (LFSD) [2], which performs iterative detection and decodes in turbo Multiple Input Multiple Output (MIMO) systems. A Fixed-complexity Sphere Decoder (FSD) is modified as List FSD (LFSD) [2], which performs iterative detection and decodes in turbo Multiple Input Multiple Output (MIMO) systems This method obtains a list of candidates for calculating likelihood information about the transmitted bits required by the outer decoder [2]. In [8] a novel MIMO detection algorithm is introduced which is called Modified Fixed-Complexity Soft-Output (MFCSO) detection This MFCSO used achieves better performance in terms of bandwidth and hardware implementation cost.
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