Abstract
In preparation for the High-luminosity LHC upgrade, the whole ATLAS inner tracker will be replaced by a new silicon detector tracker. The innermost region will be covered by silicon pixel detectors as a high density of produced particles is expected. To operate in such an environment, high-resolution sensors and a high-speed readout system are required. At the moment, the front-end readout chip prototype RD53A and a data acquisition system (the YARR system) based on a commercial FPGA board and dedicated software for quality assurance and quality control test have been developed. Due to the high density of sensor channels, the output speed from RD53A is at maximum 1.28 Gbps per line, sixteen times faster than the readout front-end chip currently used in the ATLAS pixel system. The data acquisition system needs to establish communication with 1.28 Gbps speed during the quality control tests, to validate the data acquisition path, and to optimize the procedure for data taking at high speed. From the quality control perspective this optimization allows to test large numbers of modules simultaneously exploiting the data acquisition speed reducing the time needed for the tests. Another challenging point is the novel concept of readout structure planned for the operation after installation. In High-luminosity LHC, large parts of the ATLAS data acquisition system infrastructure are going to be shared among all sub-detectors, using FELIX systems, while current ATLAS data acquisition systems are dedicated for each sub-detector. This means that all processes done in the present data acquisition system hardware need to be overhauled into software running on the new data acquisition system. To minimize the differences between the data acquisition system for operation and quality control test, we introduced the prototype FELIX system into the data acquisition path of the YARR system. In this proceeding, an established data acquisition structure for quality assurance and quality control test of the new pixel detector is introduced, and results from basic quality control tests of the pixel detector with the new readout chip are presented.
Highlights
The Large Hadron Collider (LHC) at CERN is the world’s highest energy particle accelerator
Upgrade of the ATLAS detector, the current inner detector is going to be replaced by new silicon based inner trackers (ITk) consisting of pixel and strip detectors
While the current pixel system consists of about 2000 modules, the ITk pixel system will be composed of roughly 9200 modules
Summary
The Large Hadron Collider (LHC) at CERN is the world’s highest energy particle accelerator. A data-acquisition (DAQ) system, so called YARR (Yet Another Rapid Readout), for QA/QC test of the prototype of front-end readout chip (RD53A) has been developed based on the PCI Express (PCIe) board. For Run 3, FELIX is implemented on FLX712 [4] which is an ATLAS custom board based on a Xilinx Kintex UltraScale FPGA (Figure 2) It has 48 optical links to communicate with detectors, and 16 PCIe lanes to communicate with the host PC. The readout chain described here has been constructed with VC709
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