DAP attack modelling of first degree

Abstract

This work present first order DPA attack based on correlation coefficients on HDL models of cryptographic processors using symmetric ciphers GOST 28147-89 and mCrypton and processing data in masked representation. A system for DPA attack modeling was created, including power consumption analyzer, processing data about layout parasitic interconnections of elements and connections, time-annotated post-place-and-rout information, processor internal elements activity data. As the result of the analysis, we obtained power consumption traces, serving as input for the first order DPA attack based on correlation coefficients. Based on modeling results of the attack on HDL models of the cryptographic processors and architecture features of the processors, we conclude that used processors cores have increased resistance to the attack. As the result, we can recommend the cores of the processors to be used in resource-constrained devices (smart-cards, cryptographic tokens, mobile devices) with higher resistance to first order DPA attack.