Damascene copper interconnects with polymer ILDs

Abstract

On-chip interconnects with copper metallization and polymer interlevel dielectrics (ILDs) have the lowest R-C delay, lowest parasitic coupling and highest electromigration resistance of currently proposed room temperature material sets. Patterning of such interconnect structures requires either damascene patterning (chemical-mechanical planarization (CMP) of copper deposited into trenches and via reactive ion etching (RIE) into the polymer) or elevated temperature RIE patterning of the copper. In this paper we present the dual damascene patterning of copper on low dielectric constant polymers like divinylsiloxane bisbenzocyclobutene (DVS bis BCB) and parylene- n. In particular, we present and discuss various RIE polymer etch masks and CMP polish stops that have been utilized in this work (such as PECVD silicon nitride, PECVD silicon dioxide and tantalum) and the results with different pads and slurries. Emphasis is placed on achieving a planar copper CMP with a minimum amount of polish stop and polymer ILD erosion, as well as attaining low contact resistance. Difficulties in achieving these desirable features with relatively soft low dielectric constant polymers are presented, with contact resistivity in the mid 10 −9 Ω-cm 2 having been achieved to date.