DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs

Abstract

Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded random access memories (RAMs). Fault-location ability of test algorithms executed by a BISR circuit has heavy impact on the repair efficiency of the BISR circuit. This paper proposes a defect-aware BISR (DABISR) scheme for single-port RAMs (SPRAMs) and multi-port RAMs (MPRAMs) in system chips. Multiple RAMs can share a DABISR such that the area cost of DABISR is drastically reduced. We also present two defect-location algorithms (DLAs) for identification of bridge defects between word-lines and bit-lines of MPRAMs. The DABISR can perform DLAs to locate bridge defects such that it can provide high repair efficiency. For example, simulation results show that if a faulty two-port RAM has 20% inter-port faults, the DLAs can help to gain 8.4-14.4% increase of repair rate for different redundancy configurations. In comparison with an existing shared BISR scheme, however, the DABISR only incurs about 0.34% additional area overhead to support the function of DLAs.