Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs

Abstract

A modern system-on-chip (SOC) may become one of the dies of a three-dimensional (3D) IC using through-silicon via (TSV). Built-in self-repair (BISR) techniques have been widely used to improve the yield of RAMs in a SOC. This paper proposes a memory BISR allocation scheme to allocate shared BISR circuits for RAMs in a SOC die such that the test and repair time and the area of BISR circuits are minimized. To minimize the test and repair time of RAMs in the pre-bond and post-bond test phases, a test scheduling engine is used to determine the pre-bond and post-bond test sequences of RAMs under the corresponding test power constraints. Then, a BISR-circuit minimization algorithm is proposed to reduce the number of required shared BISR circuits for the RAMs under the constraints of pre-bond and post-bond test sequences and distance between the BISR circuit and served RAMs. Simulation results show that in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit), 35% area reduction can be achieved by the shared BISR scheme planned by the proposed allocation technique under lmm distance constraint, and 500mW and 600mW pre-bond and post-bond test power constraints, respectively.