Abstract
In this study, we have calculated the tunnelling current through ultra thin gate oxides for MOS structure. In the aim to reduce the large gate leakage while scaling SiO 2 down oxide thickness, it has become necessary to use high-k gate dielectrics. We have used HfO 2/SiO 2 dual layer as gate oxide. According to the importance of these alternative gate dielectrics, it becomes essential to take into account the existence of electron trap at the HfO 2/SiO 2 interface. The gate current of n poly-Si/HfO 2/trap/SiO 2/p Si substrate capacitors is underestimated for low voltage if the effect of traps is not taken into account. The influence of trap parameters like width, depth and material masse on gate current has been examined.
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