Challenges in Evaluating Thickness, Phase, and Strain in Semiconductor Devices Using High Resolution Transmission Electron Microscopy

Abstract

Abstract The aggressive scaling of metal oxide semiconductor field effect transistor (MOSFET) device features, including gate dielectrics, silicides, and strained Si channels, presents unique metrology and characterization challenges to control electrical properties such as reliability and leakage current. This paper describes challenges faced in measuring the thickness of thin gate oxides and interfacial layers found in high-K gate dielectrics, determining Ni silicide phase in devices, and characterizing strain in MOSFETs with SiGe stressors. From case studies, it has been observed that thin layers (gate oxide, high-K film thickness, and interfacial layer) can be measured using high-resolution transmission electron microscopy (HRTEM) with good accuracy but there are some challenges in the form of sample thickness, damage-free samples, and precise sectioning of the sample for site-specific specimens. Complementary information based on HRTEM, annular dark field, and image simulation should be used to check the accuracy of thin gate dielectric measurements.