Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

Abstract

A CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm.