Abstract
fcCSP packaging was historically based on solder interconnects. The continued drive towards higher I/O and shrinking package sizes has lead to very dense bump pitches which exceed those of CPUs. At area array bump pitches below 150 um, solder bumps require very complex HDI or ABF-BU substrates which make them unaffordable for the mobile application space. Cu pillars are slim and tall when compared to solder bumps and thereby provide more space between interconnects at the same pitch. This increased space can be utilized on the substrate side to relax the trace pitch and/or to route escape traces between the pillars. The net effect is a simpler and lower cost substrate. The higher stand-off facilitated by the tall pillars allows undermolding which is significantly more cost effective than capillary underfilling. Here, design rules,process flow and reliability data will be presented from volume manufacturing processes. Modeling data for low K die with Cu pillar will be discussed as well.
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