Abstract
Connected component detection and labeling is an essential step in many image analysis techniques. In this paper, we propose a systolic VLSI architecture for labeling connected components in an image. The architecture has been designed and verified using Cadence Verilog-XL and also implemented on a rapid prototyping system using FPGA's connected as a linear systolic array. Although, the algorithm has a time complexity of O(N/sup 2/), this is in term of the actual clock cycle which is 15 ns. The proposed hardware can process a 128/spl times/128 image in 0.992 ms and uses 128 processors whereas the MPP requires 94.6 ms with 16384 processors.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
