A high speed systolic architecture for labeling connected components in an image

Abstract

Connected components detection and labeling is an essential step in many image analysis techniques. The efficiency of the connected components labeling algorithm is critical for many image processing and machine vision applications that require real time response. The advances in the areas of parallel processing and VLSI technology can be exploited in designing hardware algorithms of high speed and throughput. The authors propose a systolic algorithm and architecture for finding connected components in an image. The architecture is simple and can be implemented as a special purpose VLSI chip. Although, the algorithm has a time complexity of O(N/sup 2/), this is in terms of the actual clock cycle which is estimated as 25 nano seconds. The proposed hardware can process a 128*128 image on 0.85 msec and uses 128 processors where as the MPP requires 94.6 msec with 16384 processors. The only special purpose hardware that exists due to X.D. Yang (1988) requires 300 msec to label a 512*512 image which can be accomplished in about 13.5 msec using the authors' proposed hardware. >