Cryogenic Phase-Locking Loop System Based on SIS Tunnel Junction

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An ultra-wideband cryogenic phase-locking loop (CPLL) system is a new cryogenic device. The CPLL is intended for phase-locking of a Flux-Flow Oscillator (FFO) in a Superconducting Integrated Receiver (SIR) but can be used for any cryogenic terahertz oscillator. The key element of the CPLL is Cryogenic Phase Detector (CPD), a recently proposed new superconducting element. The CPD is an innovative implementation of superconductor–insulator–superconductor (SIS) tunnel junction. All components of the CPLL reside inside a cryostat at 4.2 K, with the loop length of about 50 cm and the total loop delay 5.5 ns. Such a small delay results in CPLL synchronization bandwidth as wide as 40 MHz and allows phase-locking of more than 60% of the power emitted by the FFO even for FFO linewidth of about 10 MHz. This percentage of phase-locked power three times exceeds that achieved with conventional room-temperature PLLs. Such an improvement enables reducing the FFO phase noise and extending the SIR operation range.Another new approach to the FFO phase-locking has been proposed and experimentally verified. The FFO has been synchronized by a cryogenic harmonic phase detector (CHPD) based on the SIS junction. The CHPD operates simultaneously as the harmonic mixer (HM) and phase detector. We have studied the HM based on the SIS junction theoretically; in particular we calculated 3D dependences of the HM output signal power versus the bias voltage and the LO power. Results of the calculations have been compared with experimental measurements. Good qualitative and quantitative correspondence has been achieved. The FFO phase-locking by the CHPD has been demonstrated. Such a PLL system is expected to be extra wideband. This concept is very promising for building of the multi-pixel SIR array.