Cross-layer inference methodology for microarchitecture-aware fault models

Abstract

Fault injection attacks are considered one of the major threats to cyber–physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modeling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different abstraction levels, which will help in designing suitable countermeasures at reasonable cost. We also present a suite of experiments that works as a proof of concept to validate the proposed methodology.