Abstract
The dc transport properties of high-temperature superconducting Josephson junction arrays were investigated. Each array had the same design of 50 junctions in series, with each junction formed from a Y Ba2Cu3O7−x (YBCO) grain boundary grown on an engineered MgO step-edge substrate. The variation of critical current was analysed and modelled. Comparisons were made on the average and one sigma standard deviation, σ, of Ic values for arrays fabricated both on the same chip and a different chip. For arrays containing 2 μm wide junctions, the typical values of σ were 20–35%. Increasing the junction width reduces σ to 8–15% in arrays with 4 μm wide junctions, qualitatively consistent with the prediction using a model of multiple channels across the width of the junction.
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