Abstract
In this paper, we present a new method for the design of an n-bit synchronous binary up counter in quantum-dot cellular automata (QCA). This method is based on the JK flip-flop which almost always produces the simplest combinational logic in traditional sequential circuits. We implement a new QCA architecture for the JK flip-flop. Compared to the existing QCA JK flip-flop, the majority gate count, cell count, clock cycle count, and area of our QCA JK flip-flop are reduced by 57.1%, 88.1%, 55.6%, and 92.0%, respectively. Based on our QCA JK flip-flop, a method of extending state cells is proposed to design the QCA layout of the n-bit counter, such that all the clock cycle counts between any two state cells become 1. This feature can ensure that one count just takes one clock cycle, in existing methods, however, one count needs to take n−1 clock cycles. Comparisons indicate that, by applying our method, the hardware requirements (i.e., complexity and area) for QCA n-bit counter can be greatly reduced.
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