Abstract

Power analysis attack is a form of side channel attack which can recover the key of a cryptographic algorithm running on some device. In this work we propose CAD based methodology to perform power analysis on pre-silicon gate-level netlist of cryptographic algorithm. We first build a new leakage model of the critical component present in crypto design by approximating it’s dynamic power consumption from the toggle count information. Then using the power model we perform power attack to recover key using power trace of crypto design. We validated our methodology on PRESENT like cipher structure and also compared our leakage model with popular Hamming distance and Hamming weight models, where we found our model requires very less number of power traces to recover keys with high correlation. We further extended our model to work by counting the number of toggles, that can be exploited by the circuit designers to early detect if their crypto design is vulnerable to any leakage or by tool developers to induct security awareness in their flow. Finally, we integrated our methodology with hybrid testing framework for first order side channel analysis to certify crypto-implementations from pre-silicon power analysis.

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