Cost model driven test resource partitioning for SoCs

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The main factors contributing to the cost of system-on-a-chip (SOC) manufacturing tests are the required number of tester pins, the test application time, the tester memory requirements and the area overhead required by the test resources. These factors contribute with different weight, depending on the cost model of each SOC. Several methods have recently been proposed to optimise each of these factors, however none of the existing methods employs an objective function derived from the actual cost model of each product. Proposed is a genetic algorithm-based test cost optimisation method, which enables the test designer to target directly the solutions matching the test cost model specific to each SOC.