Correction for etch proximity: new models and applications

Abstract

Short-range etch proximity effects increase intra-die CD variability and degrade the IC performance and yield. Tight control of the etch bias is an increasingly critical factor in realizing the ITRS technology nodes. The 2000 technology nodes revision added a new category, the post-etch 'physical' gate length metric, that is 9 - 17% smaller than 'in-resist' gate length. We present new etch proximity correction methods and models designed to reduce negative impact of etch-induced CD variability and increase uniformity of the controlled over- etching. Resolution Enhancement Technologies (RET) design correction methods typically employ 'lumped' process models. We found that an alternative methodology based upon separation of the process factors and the related models may yield better accuracy, performance, and better suit the design and process optimization flows. The contributions from the reticle, the optics, the wafer, and etch are individually determined and then used either separately or in aggregation for the most flexible and optimum correction of their respective contributions. The etch corrections are based on the Variable Etch Bias model (VEB model). This semi-empirical model requires experimental CD information to be collected from the test patterns under fixed process conditions (point-process model). It demonstrates excellent fit to the early experimental CD-SEM data gathered to date, which spans a variety of layout features and process conditions. The VEB model works in conjunction with Calibre<SUP>R</SUP> software system's Variable Threshold Resist-Extended (VTR-E) model, however the etching is modeled separately from the optics and the resist processing. This yields better understanding and more accurate explanation of the experiments than those that are produced by the 'lumped' process modeling. The VEB model explains etch- induced bias in terms of the following three proximity characteristics or variables: effective trench width (or pattern separation), pattern density, and effective line width (or pattern granularity). We synthesized and studied their integral representations. Performance fitness of the various weighting, smoothing, and anisotropic integral kernels and their parameters were studied to correctly reflect the etch bias behavior on silicon. We found that depending on the resist composition and layer types (poly or metal), the etch bias can sometimes be explained only by one or two (out of three) proximity variables. The aperture and microloading etch effects are studied and shown to be correctly reflected in the model. We demonstrate how model-based corrections improve CD uniformity of the poly and metal layers by compensating for the iso/dense and inverse-iso/dense biases. More complicated 2-D proximity effects are also captured, which is confirmed by the comparison of the SEM images to the simulations.