Abstract

Today's complex, deep submicron system-on-chip (SOC) designs, with their smallest feature sizes, increased densities, higher frequencies, and lower supply voltages, have made noise coupling at the packaging and substrate level, key issues for wireless designers of ICs. Until recently, designers have been forced to use rule-of-thumb methodologies to guard against crosstalk at the substrate and packaging level. New substrate modeling and package modeling analysis tools outline in this work have made it possible for designers to understand the effects of noise coupling across their chip's substrates and packaging, and to address the problem early in the design cycle. Finally, transient voltages are a fact of life in telecommunications equipment. The increase complexity of semiconductors has made them more sensitive to the effects of overvoltage due to decreasing geometries. In this work, the authors suggest the selection of protection circuits.

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