Control of gate—Drain avalanche in GaAs MESFET's

Abstract

The onset of gate-drain avalanche imposes an important fundamental constraint on the drain voltage swing, and hence, on the output power of GaAs FET's. In this paper we show that recognition of the role of surface depletion and proper attention to channel design can yield avalanche voltage factors of 2-3 above bulk values. The appropriate design strategy is minimization of the undepleted epitaxial charge per unit area (Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">u</inf> ) between gate and drain, which, in turn, dictates a gate-notch depth approximately equal to the surface zero-bias depletion depth. A simple lateral spreading model is proposed which predicts that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{L} \sim 50Q\min{u}\max{-1}</tex> , where V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> is the gate-drain avalanche voltage and Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">u</inf> is measured in units of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> electrons/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This prediction is supported by a large body of experimental dc and pulse data, although considerable scatter is observed which we have attributed to epi charge nonuniformities, premature avalanche at the rough edges of AI gates formed by a liftoff process, and surface charging variations associated with dielectric passivation. The observed dependence of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> on epi charge rather than on doping level, as predicted for bulk avalanche, provides convincing evidence for nonbulk two-dimensional avalanche in the thin-film ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q_{u} &lt; 2.3</tex> ) FET geometry. In thick films ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q_{u} &gt; 2.6</tex> ), on the other hand, it is found that the bulk avalanche predictions are reasonably accurate. In terms of saturated epi current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</inf> , the bulk regime corresponds to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_{s} &gt; 450</tex> mA/mm and the lateral spreading (thin-film) regime to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_{s} &lt; 400</tex> mA/mm. Finally, we have found that gate-drain avalanche is the major cause of output saturation as a function of drain potential in power GaAs FET's.