Abstract
In this work, the development of the control algorithm for multilevel converter using Xilinx system generator has been made. A reduced component count five level converter is proposed and configured using three level flying capacitor converter stacked with a three level diode clamped converter. This converter topology is known as Asymmetric Stacked Multilevel Converter. The proposed converter possesses nine effective states including redundant states to achieve the five levels output voltage. The Phase Disposition Pulse Width Modulation with active voltage balancing algorithm is implemented. This control algorithm takes advantage of these redundant states for generating the output voltage as well as to ensure that the capacitor voltages are balanced. Two platforms are employed for design and simulate this system, the first one was the MATLAB/SIMULINK. Xilinx System Generator is used as a second platform for implementing the control algorithm as a digital module. The simulation results showed that the required functionality of the converter was verified in both platforms.
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