Abstract
In this paper, starting from theoretical considerations on the chosen architecture, chip design and measurement results are presented for a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator for a combined GPS and Galileo low-IF receiver. The modulator chip was designed in a standard 0.25 mum CMOS technology. The designed CT quadrature bandpass SigmaDelta modulator has a power consumption of 20.5 mW with 1.8-V supply voltage, a dynamic range of 57.5 dB and 50.2 dB and a peak SNDR of 52.9 dB and 48.4 dB for GPS/Galileo, respectively. The core area of the chip is 0.37 times 0.54 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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