A Continuous-Time Quadrature Bandpass Sigma-Delta Modulator with Capacitive Feedforward Chip Design for Phase Locked Loop Controllers

Abstract

A continuous-time quadrature bandpass sigma-delta (ΣΔ) modulator consisting of a chain of integrators with weighted capacitive feedforward summation (CICFF) topology is presented for LTE-A wireless controllers. The main advantage of the proposed modulator adopts the weighted capacitor technology to save a feedforward summation amplifier, hence reduces power consumption from QVCO. The phase locked loop was implemented in tsmc 0.18 μm CMOS process. With 1.8 V supply voltage and 160 M-samples/s and - 1.0 dBm 1 MHz sinusoid, measured results have achieved a dynamic range of 56 dB, a peak SNDR of 52.8 dB, a SFDR of 59 dB, an ENOB of 8.49-bit over 2.5 MHz signal bandwidth and a power dissipation of 18.5 mW. Including pads, the chip area is 1.3×1.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .