Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

Fang Tang,Amine Bermak,Amira Abbes,Mohieddine Amor Benammar

doi:10.1155/2014/208540

Abstract

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

Highlights

State-of-the-art CMOS image sensors with mega-pixel resolution prefer using column-parallel quantization scheme in order to reduce power
Since the current signal flowing into the integration capacitor gains an signal-to-noise ratio (SNR) enhancement by 11.53 dB as G is set from 0 to 7, the proposed programmable input resistor performs as an analog front-end variable gain amplifier, without consuming extra power and chip area
The extended dynamic range equals the SNR improvement; the proposed continuous-time sigma delta (CTSD) ADC pushes the imager sensing range into the smaller signal region without expensive power consumption and chip area cost compared against conventional CMOS image sensor architectures

Summary

Introduction

State-of-the-art CMOS image sensors with mega-pixel resolution prefer using column-parallel quantization scheme in order to reduce power. Due to the high oversampling ratio (>100), the power efficiency of the conventional sigma delta ADC does not have an obvious advantage [4]. The first implemented mega-pixel columnparallel discrete-time sigma delta ADC (DTSD) based CMOS imager was presented in [5]. The front-end of the ADC in [5] is a switched capacitor circuit, which requires a high driving ability for the source follower. The proposed quantization circuit consists of a 2nd order single-ended continuous-time ΣΔ modulator and 2nd order digital integrator based decimation filter. The first integrator adopts the conventional differential amplifier which has a high power supply rejection ratio. The second integrator is realized by a single-ended autozeroed inverter amplifier to reduce the power.

Imager Architecture and Implementation

Proposed System Design

12 ADC channels

Experimental Results

Conclusion