A Two-Stage CMOS OTA with Load-Pole Cancellation

Ajmal Vadakkan Kayyil,Pavan Kumar Ramakrishna,Onnlim Yong,David J Allstot,Howard C Yang

doi:10.1109/iscas.2019.8702347

A Two-Stage CMOS OTA with Load-Pole Cancellation

Ajmal Vadakkan Kayyil, Pavan Kumar Ramakrishna + Show 3 more

https://doi.org/10.1109/iscas.2019.8702347

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Publication Date: May 1, 2019

Citations: 6

Affiliation: Oregon State University

#Operational Transconductance Amplifier #Conventional Operational Transconductance Amplifier + Show 8 more

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Abstract

A two-stage load-pole-cancelled (LPC) operational transconductance amplifier (OTA) which consumes an order of magnitude less power than a conventional Miller-compensated OTA is described. An extra stage is added to a conventional CMOS two-stage OTA to enable LPC. The concept, validated in a 0.18um CMOS process, achieves an ∼8X power reduction compared to the conventional OTA for a load capacitance of 5 pF.

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